Many electronic systems and virtually every computer includes a memory to store information. For temporary storage, many systems use random access memory (RAM) for high access speed and low cost. Several types of RAM and other memory devices have been and continue to be developed as computers and other electronic systems evolve.
To store and retrieve information using a memory, data is asserted on multiple data lines by a data source device. In a purely synchronous system, data output and capture are referenced to a common free-running system clock. The maximum data rate for such a system, however, is reached when the sum of output access time and flight time approaches the bit time (the reciprocal of the data rate). Although generating delayed clocks for early data launch and/or late data capture allows for increased data rates, such techniques do not account for movement of the data valid window (DVW, or data eye) relative to any fixed clock signal, for example due to changes in temperature, voltage, or loading.
Many memories, such as various double data rate synchronous dynamic RAM (DDR SDRAM), operate in conjunction with a data strobe to perform the memory access when data on the data lines is most likely to be valid. Data strobes are non-free-running signals driven by the device that is driving the data signals (the memory controller for WRITE operations, the memory for READ operations). For READ operations, the data strobe signals are edge-aligned with the data signals such that all data and the data strobes are to be asserted by the memory using the same internal clock signal. Consequently, the data signals and the data strobe signals are generated at nominally the same time.
A typical memory, however, does not generate data strobes in the middle of the DVW. Consequently, an external system reading the memory typically delays reading the data lines until valid data is present on the data lines. The memory controller is typically configured to delay the received strobe to the center of the DVW. Many memory systems synchronize memory accesses using delay locked loop (DLL) circuits to generate an appropriate delay following the data strobe. DLL circuits, however, consume considerable area in an already crowded integrated circuit. Using strobes and DLL circuits also presents difficulties in testing components for quality control. Further, many systems use memory controllers that control several different and independent memory modules.
In addition, to insert appropriate delays for each of the memory modules, memory controllers often include slave DLL circuits dedicated to each memory module and a master DLL circuit for controlling operation of the slave DLL circuits. Each additional DLL circuit requires additional area in the integrated circuit, thus tending to increase the size, cost, power consumption, and complexity of the memory system. The problems are exacerbated by the addition of multiple master DLL circuits, each associated with one or more bytes on a bus.